Date   : Tue, 27 Jun 2006 00:29:58
From   : jgh@... (Jonathan Graham Harston)
Subject: Re: Torch Graduate (Was: PEDL Z80 Board)

>Message-ID: <Marcel-1.53-0623105428-d07xSBG@...>

Johan Heuseveldt <johan@...> wrote:
> On Thu 22 Jun, Jules Richardson wrote:
> > were aware of the special feature in the code. If you assert the
> > interrupt line on the 1MHz bus early on in the boot cycle the MOS
> > will execute the code in the 256 byte memory mapped window in the
> > 1Mhz bus space in the memory map
>
> In the past (many years ago) I've studied the MOS 1.20 code
> extensively. I can't remember anything 'odd' that could now
> suggest something like above. OTOH, it's just like trying to find

It's quite clear:

************** clear interrupt and enable registers of Both VIAs ********

DA6BLDA #&7F    ;
DA6DINX         ;
DA6ESTA &FE4D,X ;
DA71STA &FE6D,X ;
DA74DEX         ;
DA75BPL &DA6E   ;

DA77CLI         ; briefly allow interrupts to clear anything pending
DA78SEI         ; disallow again N.B. All VIA IRQs are disabled
DA79BIT &FC     ; if bit 6=1 IRQ occured, then JSR &F055
DA7BBVC &DA80   ;
DA7DJSR &F055   ; F055 -> JMP (&FDFE) execute code in hardware
		    ; I/O area


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