Date : Tue, 20 Sep 1994 16:30:58 WET DST
From : Bonfield James <jkb@...>
Subject: R65C00 series information
Hello,
Just as people are complaining it's quiet - I happen have some info ready for
mailing. Actually I tried mailing this earlier, but a local mail switch system
was having a few daydreams and seemed to lose the UK. I claim no
responsibility for this info, but I'd be happy to hear if any of it's
incorrect. My primary source is the Rockwell data sheets.
I hope you enjoy it. Some of it's quite scary indeed.
James
PS. I'll get around to writing some info on the R6522 chip soon I hope.
The R65C00 series: R65C02, R65C102, R65C112
==========================================
This has large holes in places, but they're all filled by the advanced user
guide (I hope). The R65C00 series are the Rockwell CMOS chips. The original
6502A (and the R6502) were NMOS chips.
Differences
R65C02 R65C102 R65C112
Pin compatible with R6502 y n n
on chip clock osc. y y n
phases of clock input 2 2 1
Bus enable signal n y y
Memory Lock signal n y y
DMA support n y y
The R6502 would ignore RDY during a write operation. The CMOS ones will stop
the processor during clock 02 if RDY is 'asserted' during a write.
It gets a bit heavy after this, describing pinouts and signal (eg clock)
descriptions.
The software visible differences between CMOS and NMOS chips are:
NMOS CMOS
Indexed addressing modes Extra read of Extra read of last
across page boundary invalid address instruction byte
Execution of invalid opcodes Some terminate only All are NOPS
by reset. Results are
undefined.
Jump indirect with operand Page address does not Incs page addr and
of xxFF. increment. takes 1 extra cycle.
Read/modify/write (eg INC) One read and two Two read and one
instructions at effective write cycles. write cycle
address.
Decimal flag Indeterminate after Set to 0 after reset
reset and interrupts.
Flags after decimal operation Invalid N, V and Z. Valid flags, but adds
1 cycle.
Interrupt after fetch of Interrupt vector is BRK is executed, then
BRK instruction loaded. BRK vector is interrupt is executed.
ignored.
Instructions
I'll only describe in detail the ones that aren't on the standard 6502A.
See the table below for cycles, length, and addressing mode details.
BBR Branch on Bit Reset. There are infact 8 opcodes for this, each one
representing a particular bit. The 'opcode & 7' represents the bit
number. It takes 2 operands, but the data sheet doesn't say anything
about these! My plays with the master when writing hackrom showed that
the order is "BBR1 zp rel". The AUG specifies the length of this
instruction wrongly.
Status register : No change
BBS As for BBR, except a Branch on Bit Set.
BRA Branch always
Status register : No change
PHX Push X register onto stack
Status register : No change
PHY Push Y register onto stack
Status register : No change
PLX Pull X register from stack
Status register : N and Z (as PLA)
PLY Pull Y register from stack
Status register : N and Z (as PLA)
RMB Reset Memory Bit. Not listed in AUG at all. Eight opcodes of which the
bottom three bits encode the bit to reset (clear). Only works in zero
page addressing mode.
Status register : No change
SMB Set Memory Bit. As RMB except to set.
STZ Store Zero. Writes zero to the effective address.
Status register : No change
TRB Test and Reset Bits. With M equal to the address specified in the
operand, this stores A & M in M.
Status register : Z set if new M == 0
TSB Test and Set Bits. Stores A | M in M.
Status register : Z set if new M == 0
Opcode table
LSD 0 1 2 3 4 5 6 7
MSD BRK ORA *TSB ORA ASL *RMB0
0 implied (ind,x) zp zp zp zp
1 7 2 6 2 5 2 3 2 5 2 5
BPL ORA *ORA *TRB ORA ASL *RMB1
1 Rel (ind),y (ind) zp zp,x zp,x zp
2 2** 2 5* 2 5 2 5 2 4 2 6 2 5
JSR AND BIT AND ROL *RMB2
2 ABS (ind,x) zp zp zp zp
3 6 2 6 2 3 2 3 2 5 2 5
BMI AND *AND *BIT AND ROL *RMB3
3 rel (ind),y (ind) zp,x zp,x zp,x zp
2 2** 2 5* 2 5 2 4 2 4 2 6 2 5
RTI EOR EOR LSR *RMB4
4 implied (ind,x) zp zp zp
1 6 2 6 2 3 2 5 2 5
BVC EOR *EOR EOR LSR *RMB5
5 rel (ind),y (ind) zp,x zp,x zp
2 2** 2 5* 2 5 2 4 2 6 2 5
RTS ADC *STZ ADC ROR *RMB6
6 implied (ind,x) zp zp zp zp
1 6 2 6+ 2 3 2 3+ 2 5 2 5
BVS ADC *ADC *STZ ADC ROR *RMB6
7 rel (ind),y (ind) zp,x zp,x zp,x zp
2 2** 2 5*+ 2 5+ 2 4 2 4+ 2 6 2 5
*BRA STA STY STA STX *SMB0
8 rel (ind,x) zp zp zp zp
2 3* 2 6 2 3 2 3 2 3 2 5
BCC STA *STA STY STA STX *SMB1
9 rel (ind),y (ind) zp,x zp,x zp,x zp
2 2** 2 6 2 5 2 4 2 4 2 4 2 5
LDY LDA LDX LDY LDA LDX *SMB2
A imm (ind,x) imm zp zp zp zp
2 2 2 6 2 2 2 3 2 3 2 3 2 5
BCS LDA *LDA LDY LDA LDX *SMB3
B rel (ind),y (ind) zp,x zp,x zp,x zp
2 2** 2 5* 2 5 2 4 2 4 2 4 2 5
CPY CMP CPY CMP DEC *SMB4
C imm (ind,x) zp zp zp zp
2 2 2 6 2 3 2 3 2 5 2 5
BNE CMP *CMP CMP DEC *SMB5
D rel (ind),y (ind) zp,x zp,x zp
2 2** 2 5* 2 5 2 4 2 6 2 5
CPX SBC CPX SBC INC *SMB6
E imm (ind,x) zp zp zp zp
2 2 2 6+ 2 3 2 3+ 2 5 2 5
BEQ SBC *SBC SBC INC *SMB7
F rel (ind),y (ind) zp,x zp,x zp
2 2** 2 5*+ 2 5+ 2 4+ 2 6 2 5
LSD 8 9 A B C D E F
MSD PHP ORA ASL *TSB ORA ASL *BBR0
0 implied imm acc abs abs abs zp
1 3 2 2 1 2 3 6 3 4 3 6 3 5**
CLC ORA *INC *TRB ORA ASL *BBR1
1 impied abs,y acc abs abs,x abs,x zp
1 2 3 4* 1 2 3 6 3 4* 3 7 3 5**
PLP AND ROL BIT AND ROL *BBR2
2 implied imm acc abs abs abs zp
1 4 2 2 1 2 3 4 3 4 3 6 3 5**
SEC AND *DEC *BIT AND ROL BBR3
3 impied abs,y acc abs,x abs,x abs,x zp
1 2 3 4* 1 2 3 4* 3 4* 3 7 3 5**
PHA EOR LSR JMP EOR LSR *BBR4
4 implied imm acc abs abs abs zp
1 3 2 2 1 2 3 3 3 4 3 6 3 5**
CLI EOR *PHY EOR LSR *BBR5
5 impied abs,y acc abs,x abs,x zp
1 2 3 4* 1 3 3 4* 3 7 3 5**
PLA ADC ROR JMP ADC ROR *BBR6
6 implied imm acc (abs) abs abs zp
1 4 2 2+ 1 2 3 6 3 4+ 3 6 3 5**
SEI ADC *PLY *JMP ADC ROR *BBR7
7 impied abs,y implied (abs,x) abs,x abs,x zp
1 2 3 4*+ 1 4 3 6 3 4*+ 3 7 3 5**
DEY *BIT TXA STY STA STX *BBS0
8 implied imm implied abs abs abs zp
1 2 2 2 1 2 3 4 3 4 3 4 3 5**
TYA STA TXS *STZ STA *STZ *BBS1
9 impied abs,y implied abs abs,x abs,x zp
1 2 3 5 1 2 3 4 3 5 3 5 3 5**
TAY LDA TAX LDY LDA LDX *BBS2
A implied imm implied abs abs abs zp
1 2 2 2 1 2 3 4 3 4 3 4 3 5**
CLV LDA TSX LDY LDA LDX *BBS3
B impied abs,y implied abs,x abs,x abs,y zp
1 2 3 4* 1 2 3 4* 3 4* 3 4* 3 5**
INY CMP DEC CPY CMP DEC *BBS4
C implied imm implied abs abs abs zp
1 2 2 2 1 2 3 4 3 4 3 6 3 5**
CLD CMP *PHX CMP DEC *BBS4
D impied abs,y implied abs,x abs,x zp
1 2 3 4* 1 3 3 4* 3 7 3 5**
INX SBC NOP CPX SBC INC *BBS6
E implied imm implied abs abs abs zp
1 2 2 2+ 1 2 3 4 3 4+ 3 6 3 5**
SED SBC *PLX SBC INC *BBS7
F impied abs,y implied abs,x abs,x zp
1 2 3 4*+ 1 4 3 4*+ 3 7 3 5**
*TSB (* == New) OP Code
zp Addressing mMde
2 5 Instruction Bytes, Machine Cycles
For "Machine Cycles":
+ Add 1 in decimal mode
* Add 1 if page boundary is crossed
** Add 2 is branch occurs to different page
Misc
----
The data sheet then goes onto describe the electrical characteristics, which
I'm sure you're not bothered with. Next come the timing diagrams, which are
too hairy to detail here, and of little relevance.